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max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces ________________________________________________________________ maxim integrated products 1 19-4109; rev 0; 7/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available general description the max3816a ddc*/i 2 c extender automatically compen- sates for excess load capacitance of long dvi, hdmi, and vga cables. a single max3816a placed at the dis- play side of the link restores signal integrity bidirectionally for both ddc clock and data over 0 to 60 meters of cable. the max3816a features compensation for cable capacitance with a guaranteed range up to 3000pf, typically beyond 5000pf. the max3816a detects state- change assertion by the logical ?nd?of the source side and display side. it asserts the new state with a rail-to-rail slew-rate-limited driver capable of meeting i 2 c rise- and fall-time requirements under the full load of the cable. after assertion of the new state, a holdoff period of 2.5? prevents a subsequent state change while the cable channel settles. under full load at 100kbps, the max3816a consumes 25mw, excluding pullup resistors. it is available in a 16-pin tssop package and operates from 0? to +70?. applications front-projector dvi/hdmi inputs high-definition televisions, displays, and computer monitors dvi/hdmi cable-extender modules and active cable assemblies features ? ddc or i 2 c cable extension up to 60 meters at 100kbps for both clock and data channels ? single-sided solution requires only one max3816a at the display side ? compensates for cable capacitance, 0 to 3000pf guaranteed (8x i 2 c specification), or beyond 5000pf typical ? parallel and serial operating modes ? prevents ringing due to reflections by terminating transmission line impedance after transitions ? use with max3815 tmds equalizer to form a complete digital video extension solution ? 3.0v to 5.5v power supply ? optional voltage translation between 5v cable ddc and 3.3v display ddc levels typical application circuit (parallel mode) ordering information part temp range pin-package MAX3816ACUE+ 0 c to +70 c 16 tssop + denotes a lead-free/rohs-compliant package. pin configuration appears at end of data sheet. *ddc (display data channel) is part of the vesa standard. tmds is a registered trademark of silicon image, inc. dvi is a trademark of digital display working group. hdmi is a trademark of hdmi licensing, llc. drvr_en v cc clock_c data_c gnd_ref clock_d v ss data_d v dd ddc scl ddc sda ddc +5v connector to display dvi, hdmi, or m1 connector, < 3m 47k 47k 10 f 10 f long cable from video source: dvi, hdmi, or cat-5 cable up to 60m (200ft) v cc shield gnds ddc scl ddc sda ddc +5v shield gnds ddc gnd ddc gnd cable head or extender box v dd or v ss (see description) max3816a *to meet dvi/hdmi specifications for the ddc +5v link, the v dd side of the max3816a must be externally powered. if not applicable, connect to ddc +5v. 5v* mode v dd
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +3.0v to +5.5v, v dd = +3.0v to +5.5v, t a = 0? to +70?. typical values are at t a = +25?, v cc = +5.0v, v dd = +3.3v, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range (relative to v ss ) at v dd , v cc , clock_d, data_d, clock_c, data_c, drvr_en, mode ..................................................-0.5v to +6.0v continuous power dissipation (t a = +70?) (derate 11.1mw/? above +70?) ..............................889mw voltage range (relative to v ss ) at gnd_ref .......-0.5v to +0.5v operating junction temperature (t j ) range ....-55? to +150? storage ambient temperature (t s ) range .......-40? to +150? electrostatic discharge (esd) human body model......................................................> ?kv parameter symbol conditions min typ max units power supply supply voltage v cc or v dd see the applications information section (note 1) 3.0 5.5 v i cc v cc = 5.5v, v dd = 5.5v, 100kbps, 60pf load on cable, 10pf load on display, current into v cc pin 1.3 3.0 supply current i dd v cc = 5.5v, v dd = 5.5v, 100kbps, 60pf load on cable, 10pf load on display, current into v dd pin 4.3 7.0 ma dc to 500khz 100 supply noise tolerance dc to 60hz (series mode) 700 mv p-p clock_c, data_c, clock_d, data_d (notes 2, 3) cable side (clock_c, data_c) v cc - 0.1 v cc output-high voltage v oh display side (clock_d, data_d) v dd - 0.1 v dd v v ol v ol achieved within 1s of negative transition (see figure 1a, state 2) 0.2 0.4 v cable side 15 output-low voltage v hold after v ol is achieved, v hold is the most positive level allowed if logic level is 0 and no other driver is asserting low on the same node (series mode) display side 20 % of supply high-to-low threshold v trigih threshold used to detect high-to-low transition relative to supply (v cc for cable side, v dd for display side) 75 % of supply cable side 12.5 low-to-high threshold v trigil threshold used to detect low-to- high transition relative to supply (v cc for cable side, v dd for display side) display side 17.5 % of supply output-high-state current limit output in ramp-up mode for data_c 5.0 16.5 ma
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units 3.0v to 3.6v supply 700 1000 rise time (note 4) t r 4.5v to 5.5v supply 700 ns 3.0v to 3.6v supply 200 300 fall time (note 4) t f 4.5v to 5.5v supply 300 ns driver on-time driver asserting high or low 1750 ns driver active termination driver asserting high or low 60 transition sensing level-sense filter delay time to transition decision and assert 300 ns holdoff time t holdoff data/clock sensing off during this period 2.5 s lvttl/lvcmos control inputs (drvr_en, mode) input-high voltage v ih 2.0 v input-low voltage v il 0.8 v input-high current i ih v ih(min) < v in -1 +1 a input-low current i il v in < v il(max) -1 +1 a note 1: while the max3816a is operable over the continuous range of 3.0v to 5.5v, the ddc application requires v cc connection to ddc +5v. note 2: all levels in the cable side clock and data i/o are referenced to gnd_ref, unless otherwise noted. note 3: all levels in the display side clock and data i/o are referenced to v ss , unless otherwise noted. note 4: rise time measured 30% to 70%; fall time measured 70% to 30%. load range is 60pf to 3000pf on source side, and 10pf to 400pf on display side. pullup resistors are chosen to supply i 2 c maximum of 3ma when asserting low state. electrical characteristics (continued) (v cc = +3.0v to +5.5v, v dd = +3.0v to +5.5v, t a = 0? to +70?. typical values are at t a = +25?, v cc = +5.0v, v dd = +3.3v, unless otherwise noted.) i cc vs. v cc max3816a toc01 v cc (v) i cc (ma) 5.25 5.00 4.75 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 4.50 5.50 100kbps data, 100khz clock, includes 3.3k pullup resistors cable c load = 3000pf cable c load = 60pf i dd vs. v dd max3816a toc02 v dd (v) i dd (ma) 5.0 4.5 4.0 3.5 1 2 3 4 5 6 7 8 9 10 0 3.0 5.5 100kbps data, 100khz clock, includes 3.3k pullup resistors for 5v supply range and 2.2k pullup resistors for 3.3v supply range display c load = 330pf display c load = 10pf max3816a toc03 1v/div 2 s/div 3.3k pullup resistor at each end of cable. pulldown source: 25 cmos switch signal initiated and measured at remote source. clock_c transient response with and without max3816a, 30m cable load (2350pf) with max3816a without max3816a typical operating characteristics (v cc = +5.0v, v dd = +3.3v, t a = +25?, unless otherwise noted.)
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces 4 _______________________________________________________________________________________ typical operating characteristics (continued) (v cc = +5.0v, v dd = +3.3v, t a = +25?, unless otherwise noted.) max3816a toc04 1v/div 2 s/div 3.3k pullup resistor at each end of cable. pulldown source: 25 cmos switch signal initiated and measured at remote source. clock_c transient response with and without max3816a, 30m cable load (3100pf) with max3816a without max3816a max3816a toc05 1v/div 2 s/div 3.3k pullup resistor at each end of cable. pulldown source: 25 cmos switch signal initiated and measured at remote source. clock_c transient response with and without max3816a, 60m cable load (4700pf) with max3816a without max3816a max3816a toc06 1v/div 2 s/div 3.3k pullup resistor at each end of cable. pulldown source: 25 cmos switch signal initiated and measured at remote source. data_c transient response with and without max3816a, 60m cable load (4700pf) with max3816a without max3816a max3816a toc07 1v/div 2 s/div pullup resistors: two 3.3k in parallel. pulldown source: 25 cmos switch. clock_c transient response with and without max3816a, 62pf cable load with max3816a without max3816a cable side transition time vs. cable capacitance max3816a toc08 capacitance (pf) 30% to 70% rise or fall (ns) 5000 4000 3000 2000 1000 200 400 600 800 1000 1200 0 0 6000 v cc = 5v, 3.3k pullup resistor at each end of cable rise time fall time
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces _______________________________________________________________________________________ 5 max3816a toc09 video source clock 5v/div video source data 5v/div display clock 5v/div display data 5v/div 2 s/div 50m cable on source side, 330pf capacitance on display side, v cc = 5v, v dd = 5v clock and data initiated at video source and measured at max3816a series mode transient response (3000pf cable capacitance) max3816a toc10 clock_c at max3816a 2v/div clock_c at remote client 2v/div 1 s/div reflection aberration at clock_c pin not seen at source actual signal at video source 60m cable, signal initiated at display side reflection absorbed by max3816a v hold vs. (v ss - gnd_ref) max3816a toc11 v ss - gnd_ref (v) v hold (% of supply voltage) 0.4 0.2 -0.4 -0.2 0 5 10 15 20 25 30 35 40 0 -0.6 0.6 display side (referenced to v dd relative to v ss ) cable side (referenced to v dd relative to gnd_ref) v trigil vs. (v ss - gnd_ref) max3816a toc12 v ss - gnd_ref (v) v trigil (% of supply voltage) 0.4 0.2 0 -0.2 -0.4 5 10 15 20 25 30 0 -0.6 0.6 display side (referenced to v dd ) cable side (referenced to v cc ) typical operating characteristics (continued) (v cc = +5.0v, v dd = +3.3v, t a = +25?, unless otherwise noted.)
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces 6 _______________________________________________________________________________________ pin description pin name function 1 drvr_en driver enable input, lvttl/lvcmos. set high to enable all data and clock drivers for normal operation. set low to disable drivers, permitting isolation of cable bus from display bus. 2 v cc power supply for cable side. in the ddc application, connect to ddc +5v. connect 10f or larger bypass capacitor as shown in figure 6. 3 clock_c i 2 c cable-side clock with cable driver, cmos input/output. connect a 47k pullup resistor to v cc . 4 gnd_ref cable-side ground return. connect directly to cable ddc ground wire. the max3816a circuitry uses the video source ddc gnd as a threshold reference. also connect 10f or larger bypass capacitors as shown in figure 6. 5 data_c i 2 c cable-side data with cable driver, cmos input/output. connect a 47k pullup resistor to v cc . 6 gnd_ref cable-side ground return (alternate). connected internally to pin 4 above. 7 v cc power supply for cable side (alternate). connected internally to pin 2 above. 8, 9, 10 dnc do not connect 11 v dd power supply for display side and core circuitry. connect bypass capacitor as shown in figure 6. 12 data_d i 2 c display-side data, cmos input/output. connect a 2.2k pullup resistor to v dd for v dd = 3.3v, or a 3.3k pullup resistor to v dd for v dd = 5v. 13 v ss ground for display side and core circuitry. connect bypass capacitors as shown in figure 6. 14 clock_d i 2 c display-side clock, cmos input/output. connect a 2.2k pullup resistor to v dd for v dd = 3.3v, or a 3.3k pullup resistor to v dd for v dd = 5v. 15 v ss_t must be connected to v ss for normal operation 16 mode mode setting input, lvttl/lvcmos. force high for parallel mode (normal operation) and force low for serial operation. theory of operation the max3816a has parallel and series modes. the parallel mode is preferred for applications where high tolerance to noncompliant source and sink devices is desired (noncompliant v ol from displays and noncom- pliant v ih from sources are common). further, the par- allel mode can be operated with other speed-up devices on the same bus, either active (drvr_en = hi) or in bypass (drvr_en = lo). series mode is preferred for applications where high tolerance to ground offset or noise between and source and sink is needed. series mode also isolates display circuits from transmission line reflections in very long cables, providing full isolation between cable and dis- play buses. for in-display applications, series mode can provide level shifting between the 5v cable ddc and 3.3v display internal ddc. a single max3816a is applied at the display side of the video link to compensate for excessive cable capaci- tance. the overall operation of the max3816a, for either the data or clock signal, can be summarized as follows (figures 1a and 1b). 1) high state. drivers off. level sensing on. if no client device is controlling the ?ired-and?bus from either the source or display side, all device dri- vers are off and the bus (including the max3816a) is waiting in the high state. the pullup resistors on each side are holding the bus up to v cc on the source side and v dd on the display side. 2) high-to-low transition. drivers assert low. level sensing off (holdoff). a change of state is initiated by any device driver pulling low. once the signal transitions below 75% of the power supply, the max3816a drives both the source and display sides toward ground with a low- impedance driver, level sensing is turned off, and the holdoff timer is started. the source side is pulled down to the level of the v ss . this is accom- plished using a low-impedance n-channel buffer that is designed to drive a 1 meter (60pf) to 60
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces _______________________________________________________________________________________ 7 meter (> 3000pf) cable with a controlled slew-rate. similarly, the display side is pulled down to v ss with a controlled slew rate, open-drain n-channel mos device. these buffers stay on for 1.75?. 3) low state. level sensing off (holdoff). level sensing remains off until the completion of the holdoff period, which is 2.5? on both the clock and data channels. in series mode, drivers maintain low level (at or below v hold ). either the client pulldowns sustain the level below v ol , or the max3816a sustains the level at v hold if no other driver on the same node is pulling down. this action is in support of the ?ired-and?function across source and display sides. 4) low state, drivers off. level sensing on. after the max3816a holdoff time completes, level sensing resumes. in series mode, the max3816a supports a ?ired- and?connection between source and display sides; returning to the high state is supported only when all client sources turn off. if either the source or display side releases the bus, but not both, a max3816a level-sensing buffer senses the transi- tion at v trigil , supporting the existing low state by clamping the voltage to v hold and waiting for the remaining side to release the bus. 5) low-to-high transition. drivers on. level sensing off ( holdoff). a change of state is initiated when no device is holding the bus low on both source and display sides. when both sides exceed their respective v trigil levels, the source side turns on a slew-rate controlled open-drain p-channel device, pulling up to v cc for 1.75?. simultaneously, the display side is released and the pullup resistors pull the display- side bus up to v dd , as per normal i 2 c operation. 6) high state. drivers off. level sensing off (holdoff). during holdoff, no transitions are sensed. the high state is maintained by external pullup resistors. upon the end of holdoff, when the cable and display levels are above 85%, the state machine transitions to state (1); otherwise, it waits until levels raise above 85% to transition to state (1). data, but not clock, has anoth- er exit from state (6) to (1) upon data source or data display levels dropping below 60%. i 2 c continuous clock applications are not recommend- ed for the max3816a. the max3816a is optimized for ddc applications with a noncontinuous clock. detailed description the max3816a ddc/i 2 c 2-wire extender consists of two controllers with level-shifters, cable drivers, display drivers, and level-sensing circuitry (figure 2). controllers and level shifters the max3816a functionality is governed by two con- trollers, one for clock and one for data. bidirectional signaling is fully supported on both clock and data. the primary function of the controllers is to receive the state-change information from the source- and display- side level-sense circuitry and support the ?ired-and function between the two. when the state changes, a holdoff period is timed during which the source and display drivers assert the next state, high or low, and all input sensing is ignored while i/o transients settle (figure 3). the holdoff period is approximately 2.5?. the cable transmission-line termination feature is active only during the first 1.75? of holdoff, sufficiently long enough to absorb roundtrip reflections from a 60m cable. in series mode, the clock and data controllers iso- late the source electronics from the display electronics. the cable side of the max3816a is referenced to v cc and gnd_ref, and the display side is referenced to v dd and v ss . this power scheme provides tolerance to offset and noise between the source and display devices. cable drivers the low-impedance cable drivers (figure 10) can charge and discharge at least 3000pf of capacitive cable load within the i 2 c rise and fall time limits. the drivers each incorporate a slew-rate limiter to control the amount of high-frequency energy transmitted. the cable drivers also provide a back termination imped- ance of approximately 60 to absorb transmission-line reflections returning to the driver. the cable drivers each include a high-state current-limiting feature to clamp the output current to less than 16ma. after 1.75? of driver assertion, following a decision to transition, the low-impedance drivers are turned off. subsequently, when another device asserts a new state, it does not have to work against the low imped- ance of the max3816a.
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces 8 _______________________________________________________________________________________ low state high state clock_d > 17.5% and clock_c > 12.5% clock_c ?r?clock_d < 75% notes: 1) state change conditions are in italics . transition actions are underlined. 2) the data channel state machine is identical and symmetric, except that holdoff time is 2.0 s instead of 2.5 s. also, in addition to the 85% condition to exit state 6, data has an additional exit: data_c ?r?data_d < 60%. 3) dependent on mode pin 16: mode = low for serial operation (drivers hold); mode = high for parallel operation (drivers off). holdoff timer = start holdoff timer = start 5 sense off drivers on 6 sense off drivers off 4 sense on (note 3) ramp up ramp down 3 sense off (note 3) 1 sense on drivers off 2 sense off drivers on holdoff timer = 1.75 s holdoff timer = 1.75 s holdoff timer 2.5 s ?nd clock_c ?nd?clock_d > 85% holdoff timer = 2.5 s figure 1a. clock state machine diagram locally, connect a 47k pullup resistor from clock_c and data_c to v cc . this assumes that a 1.65k pullup resistor resides at the opposite end of each channel. display drivers the display drivers (figure 11) are typical open-drain pulldown devices capable of discharging up to 400pf of capacitive load within the i 2 c fall-time limits. locally, connect a 2.2k pullup resistor from clock_d and data_d to v dd for v dd = 3.3v, or a 3.3k pullup resistor to v dd for v dd = 5v. level sense the max3816a? level-sensing circuitry monitors the incoming data for state transitions. when the clock or data signal is high and drops below v trigih , the con- troller ramps the outputs low. when the data and clock are low and both rise above v trigi l , refer- enced to gnd_ref on the source side or v ss on the display side, the output drives the level high.
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces _______________________________________________________________________________________ 9 v xx ddc v ih = 70% v xx ddc v il = 30% v xx ddc v ol (max) = 0.4v gnd gnd v xx ddc v ih = 70% v xx ddc v il = 30% v xx ddc v ol (max) = 0.4v cable/ source side (note 1) state number display side (note 1) v trigih = 75% v xx 0 s holdoff timer notes: 1) this example applies to transmission in either direction. source to display is shown. 2) v xx is used generically for the voltage at the v cc or v dd pins. v trigih = 12.5% v cc clock_c, 17.5% v dd clock_d v hold = 15% v cc clock_c, 20% v dd clock_d 0 s 1.75 s 2.5 s 1.75 s 2.5 s 1 1 24 3 5 6 figure 1b. signal waveform example showing states
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces 10 ______________________________________________________________________________________ controller and level shifter lpf gnd_ref clock_c data_c clock_d data_d mode drvr_en v ss v dd cable driver cable termination resistors v trigih v trigil level sense display driver driver_enable (internal) driver enable v cc max3816a lpf v trigih v trigil level sense cmos cmos controller and level shifter lpf gnd_ref cable driver cable termination resistors v trigih v trigil level sense display driver driver_enable (internal) driver_enable (internal) lpf v trigih v trigil level sense v cc v dd v ss v ss v ss v ss v cc v dd v dd v ss v ss v ss v cc figure 2. functional diagram
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces ______________________________________________________________________________________ 11 figure 4. holdoff with decision points shown o = decision point data clock t holdoff_d t holdoff_c figure 3. holdoff operation with max3816a without max3816a t holdoff t holdoff clock_c or data_c v trigil v trigih
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces 12 ______________________________________________________________________________________ figure 5. typical in-display application circuit drvr_en v cc clock_c data_c gnd_ref clock_d v ss data_d v dd i 2 c scl i 2 c sda display 3.3v display i 2 c bus reference to 3.3v 47k 47k 2.2k 2.2k 10 f 10 f ground plane v dd 1 f long cable from video source: dvi, hdmi, or m1 connector cable up to 60m (200ft) v cc display gnd ddc scl ddc sda ddc +5v shield gnds ddc gnd display circuit board v dd or v ss (see description) mode v ss max3816a applications information use single max3816a at display side a single max3816a is designed to achieve full 100kbps operation over 60m (200ft) of cable. in-display application, series mode when inserted at the front-end of a display, the source side of the max3816a should be powered by the source v cc (typically 5v) and ground (gnd_ref). the display-side v dd should be powered by the local dis- play supply (typically 3.3v) to level-shift and diminish the effects of supply noise and offset between source and display (figure 5). supply decoupling capacitors of at least 10? should be connected close to the max3816a between gnd_ref and v ss , as well as between gnd_ref and v cc . max3816a in-display, series mode advantages (see figure 5) long cable reach. the max3816a acts as a buffer between source and display. hence, source reflections are isolated to the source side of the max3816a, protecting display cir- cuits from reflections (stair-step waveforms). the max3816a can be turned off (drvr_en assert- ed low) to isolate source and display buses. the dis- play bus can then operate independently of source-cable loading or malfunctions. multiple max3816as can be used in parallel as an input mux to display, with only one ?n?at a time. consideration when using the level-shifter feature, as shown, and assum- ing the display 3.3v supply is off when the display is off, the display edid prom will not be able to communicate to source ddc. if required, the solution is to either place a 5v edid prom on the source side of the max3816a or derive the 3.3v v dd from the ddc +5v supply.
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces ______________________________________________________________________________________ 13 external box or cable assembly applications three implementations external to the display such as external box products or cable assemblies are shown in figures 6, 7, and 8. max3816a external to display, in series advantages (see figure 6) long cable reach. the max3816a acts as a buffer between the source and display. hence, source reflections are isolated to the source side of the max3816a, protecting dis- play circuits from possible double clocking due to stair-step waveforms caused by very long cables with reflections. the max3816a can be turned off (drvr_en assert- ed low) to isolate source and display buses. the dis- play bus can then operate independently of source-cable loading or malfunctions. also, multiple max3816as can be used in parallel as an input mux to display, with only one ?n?at a time. consideration only one series-connected max3816a is allowed on a bus. two or more series-connected max3816a ics will not function. if multiple max3816a ics are expected, use the parallel applications in figures 7 and 8. figure 6. external to display, in series drvr_en v cc clock_c data_c return clock_d v ss data_d 5v* ddc scl ddc sda ddc +5v 47k 47k 3.3k 3.3k 10 f 10 f ground plane cable head or extender box *to meet dvi/hdmi specifications for the ddc +5v link, the v dd side of the max3816a must be externally powered. if not applicable, connect to ddc +5v. long cable from video source: dvi, hdmi, or cat-5 cable up to 60m (200ft) connector to display dvi, hdmi, or m1 connector, < 3m v cc shield gnds ddc scl ddc sda ddc +5v shield gnds ddc gnd ddc gnd v dd or v ss (see description) max3816a mode v ss v dd
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces 14 ______________________________________________________________________________________ max3816a external to display, switchable series and parallel mode advantages (see figure 7) long cable reach. in parallel mode, the max3816a is very tolerant of noncompliant ddc sources and sinks. the max3816a can be turned off and bypassed if another max3816a or speed-up device is being used on the same ddc. in parallel mode, the max3816a can be used simul- taneously with other i 2 c speed-up devices. the max3816a acts as a buffer between source and display. hence, source reflections are isolated to the source side of the max3816a, protecting display circuits from possible double clocking due to stair- step waveforms caused by very long cables with reflections. in series mode, the max3816a can be turned off (drvr_en asserted low) to isolate between source and display buses. the display bus can then oper- ate independently of source-cable loading or mal- functions. consideration use a good quality cmos switch with low resistance (< 20 ) and over/undervoltage tolerance. figure 7. external to display, switchable series and parallel mode max3816a max4719 drvr_en clk_c data_c mode clk_d data_d ena long cable from source +5v byp ser par +5v +5v 47k 47k 3.3k connector to display 10 +5v 3.3k 10 series mode: drvr_en = hi (ena), mode = lo (ser) parallel mode: drvr_en = hi (ena), mode = hi (par) bypass mode: drvr_en = lo (byp), mode = hi (par) isolate mode: drvr_en = lo (byp), mode = lo (ser)
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces ______________________________________________________________________________________ 15 max3816a external to display, in parallel advantages (see figure 8) medium-long cable reach. in parallel mode, the max3816a is very tolerant of noncompliant ddc sources and sinks. the max3816a can be turned off if another max3816a or speed-up device is being used on the same ddc. the max3816a can be turned off without isolating the display from the source side, letting ddc oper- ate straight through unassisted or assisted. consideration long cable reflections can reach display circuits since the max3816a is not used as a buffer between source and display. hence, very long cables could cause dou- ble-clocking at display circuits due to stair-step rise/fall waveforms due to reflections. figure 8. external to display, in parallel drvr_en v cc clock_c data_c gnd_ref clock_d v ss data_d v dd ddc scl ddc sda ddc +5v connector to display dvi, hdmi, or m1 connector, < 3m 47k 47k 10 f 10 f long cable from video source: dvi, hdmi, or cat-5 cable up to 60m (200ft) v cc shield gnds ddc scl ddc sda ddc +5v shield gnds ddc gnd ddc gnd cable head or extender box v dd or v ss (see description) max3816a *to meet dvi/hdmi specifications for the ddc +5v link, the v dd side of the max3816a must be externally powered. if not applicable, connect to ddc +5v. 5v* mode v dd
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces 16 ______________________________________________________________________________________ v cc v cc return drivers v ss sense return back termination clock_c or data_c max3816a v dd v ss driver v ss sense clock_d or data_d max3816a v dd v ss drvr_en max3816a figure 9. clock_c/data_c equivalent interface structure figure 10. clock_d/data_d equivalent interface structure figure 11. drvr_en equivalent interface structure interface schematics
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces ______________________________________________________________________________________ 17 typical in-display operating circuits rgb/hv adc/sync tmds deserializer select image scaler and processor panel interface timing and drivers lcd, dlp, or lcos vga input hdmi/dvi-d input hdmi/dvi-d cable up to 60m or 200ft laptop video projector tmds equalizer max3815 max3816a ddc extender drvr_en v cc clock_c data_c gnd_ref clock_d v ss data_d v dd ddc scl ddc sda ddc +5v ddc +5v from source ddc scl ddc sda displaygnd drivers indisplay ddc extender one max3816a used at display side of cable in cable head, or extender box, or display display client connector (or short cable < 3m) to projector, lcd, plasma 47k 47k 3.3k 3.3k 10 f 10 f ground plane long cable up to 60 meters (200ft) dvi or hdmi cable, or cat-5 source client ddc master in video source: pc, dvd, stb v cc shieldgnds ddc scl ddc sda ddc+5v ddc gnd ddc scl ddc sda ddc+5v shieldgnds shieldgnds ddc gnd ddc gnd v dd or v ss max3816a ddc +5v ddc scl ddc sda sourcegnd drivers insource r pullup r pullup r pullup r pullup mode v ss
max3816a i 2 c 2-wire extender for ddc in dvi, hdmi, and vga interfaces maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. chip information transistor count: 5759 process: cmos max3815 tmds equalizer max3816a ddc extender pc monitor up to 60m dvi-d cable up to 3m dvi-d cable digital cable digital satellite dvd pc dvi-d extender box video source typical in-display operating circuits (continued) 16 15 14 13 12 11 10 1 2 3 4 5 6 7 mode v ss_t clock_d v ss gnd_ref clock_c v cc drvr_en top view max3816a data_d v dd dnc v cc gnd_ref 9 8 dnc dnc data_c tssop + pin configuration package type package code document no. 16 tssop u16+2 21-0066 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .

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